1. Field of the Invention
The invention relates to a voltage converting technique, and more particularly, to a time signal generating circuit and a time signal generating method for application in a multi-phase power converter.
2. Description of Related Art
FIG. 1 is a schematic diagram illustrating a multi-phase power converter in conventional art. FIG. 2 is a waveform diagram of the multi-phase power converter in conventional art. Referring to FIG. 1 and FIG. 2 together, a multi-phase power converter 1 in conventional art usually adopts design of a constant on-time architecture. The multi-phase power converter 1 is a two-phase power converter. A driving circuit 10 drives a first phase output stage to generate a first phase current (a first inductive current) IL1, and the driving circuit 10 drives a second phase output stage to generate a second phase current (a second inductive current) IL2. The first phase current IL1 and the second phase current IL2 flow into a load and generate an output voltage Vout at an output terminal of the multi-phase power converter 1. A feedback signal Vfb is related to the output voltage Vout. A comparator 12 compares the feedback signal Vfb with a reference voltage Vref to generate an error signal Xerr. A ramp generator 16 generates a ramp signal Xramp. A comparator 14 compares the error signal Xerr with the ramp signal Xramp to generate a comparing signal Xcm.
A logic control circuit 24 generates a control signal according to the comparing signal Xcm to control the ramp generator 16, a current balancing circuit 18, a first on-time generator 20a and a second on-time generator 20b. The logic control circuit 24 generates a first phase pulse width modulation (PWM) signal PWM1 according to a first phase on-time signal Ton_1, and the logic control circuit 24 generates a second phase pulse width modulation signal PWM2 according to a second on-time signal Ton_2. The driving circuit 10 controls switches UG1 and LG1 of the first phase output stage according to the first phase pulse width modulation signal PWM1, and the driving circuit 10 controls switches UG2 and LG2 of the second phase output stage according to the second phase pulse width modulation signal PWM2.
The current balancing circuit 18 determines whether each phase current is in balance according to a first phase signal LX1 and a second phase signal LX2, and sends a determination result to the first on-time generator 20a and the second on-time generator 20b. The first on-time generator 20a generates the first phase on-time signal Ton_1 according to said determination result, the control signal of the logic control circuit 24, an input voltage Vin, and the output voltage Vout. The second on-time generator 20b generates the second phase on-time signal Ton_2 by operations similar to the above.
FIG. 3 is a circuit diagram of an on-time generator in conventional art. Referring to FIG. 3, an on-time generator 20 includes a current source It, P-type metal oxide semiconductor transistors MP1 and MP2, a switch ST, a capacitor CT and a comparator 26. The current source It and the P-type metal oxide semiconductor transistors MP1 and MP2 compose a current mirror. The current source It is related to the input voltage Vin. When a pulse width modulation signal is at logic high level (“high”), an inversion signal PWMB relative to the pulse width modulation signal is at logic low level (low), such that the switch ST is cut off. Further, the comparator 26 stops counting for an on-time signal Ton only when “a current M*It (a magnification coefficient M multiplied by the current It)” is used to charge the capacitor CT until a level of a charging voltage Xc is greater than the output voltage Vout.
The first on-time generator 20a and the second on-time generator 20b in FIG. 1 have the structure similar to that of the on-time generator 20 in FIG. 3. The on-time signal Ton of each phase is used to determine a time length of the pulse width modulation signals PWM of each phase at logic high level (“high”), that is, to determine a time length of the (high side) switches UG1 and UG2 of each phase at logic high level. In view of FIG. 3, it can be known that an on-time is obtained through a calculation processing of the input voltage Vin and the output voltage Vout.
FIG. 4 is a circuit diagram applying the current balancing circuit 18 in conventional art. FIG. 5 is a waveform diagram of the related signals in FIG. 4. Referring to FIG. 4 and FIG. 5 together, the first phase pulse width modulation signal PWM1, a control signal SW1 and a first holding control signal Hold_1 are identical in terms of the phase, whereas a first sampling control signal Sample_1 is an inversion signal of the first holding control signal Hold_1. Similarly, the second phase pulse width modulation signal PWM2, a control signal SW2 and a second holding control signal Hold_2 are identical in terms of level variation, whereas a second sampling control signal Sample_2 is an inversion signal of the second holding control signal Hold_2.
The current balancing circuit 18 includes current balancing units 18a and 18b. The current balancing units 18a and 18b have the same structure. For example, the current balancing unit 18a uses an amplifier 22a and a plurality of current mirrors, and the current balancing unit 18b also uses an amplifier 22b and a plurality of current mirrors. A resistance RSN is used to convert voltage information into current information by, for example, dividing “a reference voltage Voffset minus the first phase signal LX1” by the resistance RSN.
When the first phase pulse width modulation signal PWM1 is at logic high level (“high”), the control signal SW1 is at logic high level. Each of values obtained after subtraction of the signals (information) sampled from the first phase signal LX1 and the second phase signal LX2 are calculated by the current mirrors is sent to a terminal of a resistance RCB, so that a voltage at another terminal of the resistance RCB may be latched at a value of the output voltage Vout by a buffer. A high-boundary voltage VTON_HB1 is obtained through a calculation processing of subtracting “the resistance RCB multiplied by a current IDFF1 (IDFF1=ISN1−ISN2)” from the output voltage Vout. The high-boundary voltage VTON_HB1 may replace the output voltage Vout of the on-time generator 20 in FIG. 3 to serve as a counting high-boundary voltage. The comparator 26 stops counting for the on-time signal Ton only until the level of the charging voltage Xc is greater than the high-boundary voltage VTON_HB1.
Another high-boundary voltage VTON_HB2 is obtained through a calculation processing of subtracting “the resistance RCB multiplied by a current IDFF2 (IDFF2=ISN2−ISN1)” from the output voltage Vout.
In the multi-phase power converter, whether the current of each phase is in balance needs to be considered. If the current balance is not considered, the current of one specific phase may output more current than a channel of another phase and lead to serious problems of overheat and burnout to the circuit. In addition, the current balancing unit 18a and the current balancing unit 18b have the same structure, and each of said units uses one amplifier and multiple current mirrors. In general, the amplifier includes an offset value of its own, whereas the multiple current mirrors also include offset values of their own. For example, an offset value of the amplifier 22a is 0 mV, whereas an offset value of the amplifier 22b is 20 mV; and conversion coefficients of three current mirrors of the current balancing unit 18a are 1.01, 1.01 and 0.99, whereas conversion coefficients of three current mirrors of the current balancing unit 18b are 0.99, 0.98 and 1. Because the offset values of the amplifier 22a and the amplifier 22b are already different while the multiple current mirrors also result in many offsets, the offset values of the inductive currents (IL1 and IL2) in FIG. 1 may be overly large. In other words, it is an indispensable part as to solve a current balancing issue in design of the multi-phase power converter.